Integrated circuit shapes can be patterned on a semiconductor wafer entirely by means of direct writing, electron beam (E-beam) lithography. Methods of using an E-beam to write microcircuit patterns in integrated circuit fabrication are well known in the art.
The intended pattern can be written directly onto a semiconductor wafer by first exposing a thin layer of radiation sensitive material on the wafer with a beam of electrons. Alternatively, a thin layer of photoresist on the semiconductor wafer may be exposed optically, using a mask made with an E-beam tool. Whether the pattern is directly written with an E-beam or indirectly written with a mask made with an E-beam, the E-beam tool control remains the same. See generally, U.S. Pat. No. 4,259,724 for an example of an E-beam lithography system for direct writing to expose an entire wafer. The use of a computer to generate control data and to control the E-beam is also well known. See U.S. Pat. No. 4,820,928 for an example of a computer controlled microcircuit fabrication system. E-beam lithography provides the advantage of very sharply defined patterns for very small geometric shapes. However, transferring those computer designed to a physical image on a photoresistive, or radiation sensitive layer (resist), can be both expensive and time consuming. Most of the expense associated with transforming the shape is computer operating cost, which is also generally time dependent.
Therefore, reducing computer operating time will reduce the expense associated with E-beam lithography. Several approaches have been used to reduce the time required to expose a wafer with an E-beam tool. See U.S. Pat. No. 4,147,937 for an example of a method and an apparatus for exposing a wafer by raster scan writing, i.e., a single line at a time. See also, U.S. Pat. No. 4,914,304 for an example of an E-beam exposure system that uses a shaped beam to improve exposure of different shapes. Although these prior art approaches may have reduced wafer exposure time, they did not appreciably reduce the shape conversion time, i.e., the computer time required to prepare the shapes in a design for use on the E-beam tool. Converting the design data to Numerical Control (NC) data is called postprocessing the design. NC data is used to control an E-beam tool in exposing a radiation sensitive layer. Prior art methods of postprocessing design shapes may need several hundreds of Central Processing Unit (CPU) minutes to convert one design layer into NC data. So, postprocessing a design, converting the graphics representation of design shapes to control for the E-beam tool, is a major computer bottleneck.
The flow diagram of FIG. 1 shows the steps typically taken in the prior art to convert design data into E-beam tool control data and to expose a semiconductor wafer. Each design shape is represented in a graphics language by lines, rectangles, circles, and polygons. Such a representation is characteristic of the particular shape and graphics language. It is the graphics representation of the shape that is postprocessed, converting the graphics representation to Numerical Control (NC) data for an E-beam tool. The E-beam tool uses the converted, or postprocessed, information to direct the electron beam onto the radiation sensitive layer, which writes, or exposes, the design shape into the layer. The computer running the postprocessing program (called the postprocessor) combines the graphics design 30 and key E-beam tool processing parameters 32 (called keywords) to produce NC data.
Before postprocessing the design data, the graphics language representation of the design data 30 and the keywords 32 are checked 34 for syntax errors. After verifying that there are no syntax errors, the post processor decomposes 36 each design shape into a series of edges and then labels 38 each edge. An edge is part of the shape's perimeter and is normally a straight line connecting two vertices on the shape. Each converted edge is labeled 38 according to its position on a shape as a top, bottom, right or left edge. The postprocessor then applies 40 keywords that describe shape compensation, known as etch biases, to the edges. An etch bias is a compensation for the distortion to a design shape that occurs while writing and forming the final shape. Next, the postprocessor transforms 42 the edges from the graphics language grid (a unit of measure) to the E-beam tool grid. The postprocessor combines any butting or overlapping transformed edges (called unioning 44 the shapes or edges). When two edges are unioned, the unioned edges form a single, common edge.
After unioning the edges, the postprocessor fills 46 the shapes. Reconstructing a shape out of one or more types of basic polygons, e.g., rectangles, such that the reconstructed shape is, as nearly as possible, identical to the design shape is called "filling the shape." The reconstructed design shape is said to be filled with fill polygons or fill rectangles. See U.S. Pat. No. 4,554,625 for an example of a method of producing nonoverlapping rectangles to fill a shape.
The fill rectangles generated during the fill 46 provide the E-beam tool with control data to direct the E-beam to expose a rectangular area. For examples of rectangle generators, see, "Method and Apparatus for Digital Control of E-Beam Pattern Writing as Applied to Subfield and Vector Equipment," in the March 1980 IBM Technical Disclosure Bulletin page 4583, and see, "Method and Apparatus to Provide Rapid Interpretation of Digital Source Information During Electron-Beam Pattern Writing of Rectangular Shapes," in the April 1982 IBM Technical Disclosure Bulletin page 5681.
After the fill 46, the filled shapes, i.e. the fill rectangles, are proximity corrected 48 for proximity effects. Proximity effects are created by electrons being scattered while traveling to, from and in the resist. These scattered and reflected electrons partially expose the resist up to several micrometers from their intended point of impact (called the scattering radius) causing over exposure of surrounding shapes. Proximity correction 48 means adding control information to the fill rectangles to adjust the length of time that the E-beam exposes the resist. For example, a fill rectangle, when exposed, may cause interference with adjacent fill rectangles known as blooming. Blooming causes "fuzzy" edges and unintentionally filled notches because rectangles become overexposed. Blooming can be reduced by reducing beam exposure time for adjacent rectangles. Since proximity correction may require calculating a value for each fill rectangle with respect to each fill rectangle within its scattering radius, there may be several calculations required for each fill rectangle. Consequently, calculating proximity correction values may require as much or more CPU time as filling the design shapes.
After proximity correction, the fill data is gray-spliced 50. Gray-splicing is done because the E-beam deflection field is much smaller than an integrated circuit chip. So, the integrated circuit chip is divided into subfields, which are slightly smaller than the E-beam's deflection field. When the shapes in a subfield are written, any shapes lying on or spanning subfield boundaries may be partially written. To maintain a spanning shape's edge definition, the exposure from each subfield is overlapped into its adjacent subfield and the exposure time in the overlap is reduced. Thus, because a spanning shape is partially exposed in the overlap from each subfield, it is said to be grayed. Since the result of overlapping the grayed portions of a spanning shape splices the shape's pieces together, the shape is said to be gray-spliced.
Once gray-splicing (also spelled grey-splicing) is complete, the fill data is encoded and passed 52 to the E-beam tool as NC data. NC data is a series of commands used to control an E-beam tool, directing the tool to expose the radiation sensitive layer in a predetermined set of steps, at a predetermined exposure level. In one prior art method, fill rectangles are further reduced into one or more sub-areas called spots, each of which will be written by a vertical or horizontal raster scan. When the fill data is encoded as NC data, each fill rectangle is stored as NC data in a storage area called the pattern buffer. The exposure level is the proximity corrected value from 48 and is part of this NC data.
After the design data is converted to NC data, the E-beam tool writes 54 the design onto a wafer by exposing each fill rectangle onto a radiation sensitive layer. Once every fill rectangle has been exposed, the design shape will have been written onto the layer. The exposed pattern can be developed similarly to photodeveloping. After developing the resist, the wafer is etched, implanted or otherwise similarly altered to imprint the pattern onto the wafer. So, the NC data for E-beam tool is encoded from the data generated in the fill 46, proximity correction 48 and gray-splice 50. Since, during the fill, the computer must treat every shape as a puzzle in which the computer must both create the pieces and then fit them together; the fill 46 often accounts for a large portion of CPU time and may produce a large volume of data. Because the pieces created in the fill must be examined and, when necessary, corrected for proximity effects, proximity correction 48 may account for more CPU time and produce more data than the fill 46. Gray-splicing, which is done after proximity correction, may result in still a larger data volume and may account for the largest usage of CPU time.
A semiconductor chip, typically, has several layers of shapes, commonly known as levels that are overlaid to form micro circuits. These layers are commonly called mask levels because of the way the layers' patterns were transferred onto the chip, i.e. optically, by exposing photoresist with light directed through a mask. Although some mask levels may still be made with an optical tool, a single design may also require several levels that must be independently converted to E-beam control data. Additionally masks for optically exposed levels may be created using the same E-beam tool. Mask levels are also classified as positive or negative (also called reverse image) levels. The design shape is the intended image on a positive mask. Thus, a rectangle in the design would be an opaque rectangle on a positive mask. Conversely, a negative mask has a negative image of the design. So, a rectangle on the design would be a transparent rectangle in an opaque field on a negative mask.
The steps of filling, proximity correcting and gray-splicing each mask level are major CPU bottlenecks that may take several CPU hours each. The CPU through-put times tend to increase with N.sup.2, where N is the number of shape edges. Since each circuit has several design shapes, and since the number of edges is directly related to the number of design shapes, CPU through-put is related to the number of circuits in the design. For a complex design, the time required to fill, to proximity correct or to gray-splice a single mask level exceeds the average time between CPU failures, known as the CPU's mean time to fail. Thus, the number of circuits allowed on an integrated circuit chip could be limited by factors such as the CPU's mean time to fail rather than the E-beam tool's other physical limitations. Reducing the time required in these bottlenecks would provide a significant improvement over slow prior art post processing methods. A prior art approach to reducing the data volume has been to add a data compaction subsystem called the E-beam system's macro buffer. The macro buffer is part of the E-beam tool's storage, dedicated to storing NC data for repetitive patterns known as "User Defined Macros" (UDMs). An occurrence of a cell in a design is called the cell's transform because the cell is transformed from the cell's coordinate system to the design's coordinate system. Thus, an occurrence of a UDM in a design is called the UDM's transform. When a macro buffer is employed, the macro transforms are replaced with macro read commands that are merged with the NC data for the remaining design (non-macro) shapes in the pattern buffer. When the E-beam tool encounters the macro read command in the pattern buffer, the tool retrieves the UDM from the macro buffer and executes the NC data on the UDM.
The macro buffer takes advantage of a repetitive characteristic inherent in most designs. That repetitive characteristic results from a basic precept of logic design that any logic function can be carried out entirely in NOR gates (or NAND gates). Designers follow this basic precept by limiting the number of unique circuits they create in designing a complex integrated circuit chip. Even on a very complex chip, the number of unique circuits may be less than 100. Usually each circuit is created once ("laid out") as a cell. Shapes on each layer within that cell may be repeated as a UDM for each macro transform. By maintaining the design's nesting (reusing macros), each cell is postprocessed once and the UDM placed in the macro buffer. Whenever the E-beam tool is to write the cell, the UDM is retrieved from the Macro buffer. For a chip such as a 1 Mbit Random Access Memory (RAM), storing one million occurrences each of a RAM cell with, say, 15 fill rectangles requires a large pattern buffer. For the same 1 Mbit RAM, a macro read command to call the RAM memory cell UDM would need a much smaller pattern buffer. Thus, the macro buffer provided a significant data compaction advantage.
However, very often in the prior art, proximity effects disrupted the uniformity of a repeated UDM because the proximity effects on fill rectangles in a macro depend not only on shapes within the macro, but also on the macro's placement with respect to adjacent rectangles and Macros. So, some UDMs have proximity effects that depend on placement and, therefore, require placement dependant proximity correction.
Gray-splicing also is placement dependent for each UDM. Some UDM transforms may not require gray-splicing, while other transforms have unique placement or gray-splicing requirements. In prior art postprocessors, these placement dependent UDMs were not left in the Macro buffer. Instead, they were unnested before fill and, the unnested, former UDM shapes were filled, proximity corrected, gray-spliced individually and placed in the pattern buffer, causing the pattern buffer to swell.
One method of data compaction that addressed varying proximity correction for a UDM is disclosed in "Scheme for Proximity Correcting Repetitive Design Features," in the October 1987 IBM Technical Disclosure Bulletin pages 436-7. The disclosed scheme or method was to strip out of the UDMs all rectangles requiring proximity correction. The stripped UDMs were then placed in the Macro buffer, and the stripped rectangles were proximity corrected and placed in the pattern buffer. This was an improvement over unnesting every UDM transform and placing the unnested data in the pattern buffer, but, it still resulted in high data volume and correspondingly awkward data handling problems.
Compounding these obstacles to maintaining data compaction are the additional problems that occur on a negative mask. Making a negative mask requires filling the area around the design shapes instead of filling the design shapes. While the design shapes themselves may be identical for two transforms of a cell, the fill for the area around the shapes may not be. If, for example a repetitive array cell has transforms along the array edge with shapes that intrude into the cell area, but do not touch any of the cell's rectangles, then the fill for the transforms of the cell along that edge will not be identical to the fill for other array cell transforms.
Additionally, proximity effects may not be identical even between array edge cell transforms. Usually, these edge cells are unnested and converted to NC data as non macros. The more the unnesting of Memory array cells that is required, the more the efficiency of the macro buffer is reduced, as is the advantage provided by the macro buffer.